example (nand,or and xor) in vhdl

NAND:-
library IEEE;
use IEEE.std_logic_1164.all ;
entity NANDGATE is
 port (a : in std_logic;
b : in std_logic;
x : out std_logic ) ;
end entity NANDGATE ;
architecture RTL of NANDGATE is
begin
 x<=a nand b;
end architecture RTL ;

OR:-
library IEEE;
use IEEE.std_logic_1164.all;
entity or is
port ( a : in std_logic;
b: in std_logic;
z: out std_logic ) ;
end or ;
architecture dataflow of or is
begin
z<= a or b;
end dataflow;

XOR:-
library IEEE;
use IEEE.std_logic_1164.all;
entity xor is
 port( a: in std_logic;
b:in std_logic;
z:out std_logic );
architecture dataflow of xor is
beginz<= [a and (not b) or (not a) and b ] ;
end dataflow ;